The present invention relates to the field of electrical interconnections in semiconductor devices and more particularly to a process for improved step coverage of metal into plug filled vias. Semiconductor devices typically include vias of uniform cross section extending through an insulator or dielectric which when filled with metal become plugs which interconnect layers of an integrated circuit. The vias extend through an insulating layer or dielectric such as silicon dioxide and typically form a square corner at the intersection of the via with the dielectric. The practical removal of the metal layer used to form the plug requires that the metal be etched below the upper surface of the dielectric. The successful deposition of a second metal layer on the dielectric to contact the plugs requires that good step coverage is achieved at the vias. In the past it has been difficult to achieve this good step coverage, i.e., there is often excessive thinning of the second metal layer which can cause various problems. Thus a need exists for a process that reduces the difficulty of achieving good step coverage of metal into plug filled vias.